library verilog;
use verilog.vl_types.all;
entity Expansion_Function is
    port(
        Expansion_Function_Input: in     vl_logic_vector(32 downto 1);
        Expansion_Function_Select: in     vl_logic;
        Expansion_Function_Output: out    vl_logic_vector(48 downto 1);
        Expansion_Function_Finish_Flag: out    vl_logic;
        clk             : in     vl_logic
    );
end Expansion_Function;
